(1) Field of the Invention
The present invention pertains to bidirectional asynchronous data transmission and more particularly to a circuit for controlling said asynchronous data transmissions between a data processing system and a data terminal.
(2) Description of the Prior Art
Data processing systems can transfer data from their memory units at high rate of speed, typically in the microsecond range. On the other hand, data terminal equipment has a potentially lower transfer rate usually in the millisecond range. Therefore, when the data processing system transmits information to a data terminal, the data processor of the processing system incurs a great deal of dead-time or time during which the processor must wait for the terminal due to the disparity of transmission times. Data terminal devices range from teleprinting devices providing a hard copy to CRT's which provide information displayed upon a screen.
The information transmission between a processor and a data terminal takes the form of a parallel transmission called a data word. The processor may transmit a data word to a data terminal device and then wait for the data terminal device to print or display that word before transmitting subsequent words. This is a very inefficient transmission scheme since the processor incurs considerable dead-time while waiting for the data terminal to print or display the word. Some data processing systems alleviate this problem by initiating a word transmission to several data terminals and then returning to the first data terminal to initiate a second transmission to it, etc. However, the drawback of that configuration is that the processor must establish proper protocol to transmit to the data terminal. Establishing protocol requires time for each data terminal and thereby the data processor spends considerable time in establishing protocol to the plurality of data terminals.
As a solution to this problem, buffering is introduced between the data processor and the data terminal device. This buffering forms a part of the data transfer control circuit. Logic is required to control the operation of this buffer along with the receiver transmitter device for converting serial data to parallel and vice versa. As an option to providing logic the data processor may control each step of the data transfer control circuit. For the same reason that was mentioned above this scheme is also inefficient. Therefore, hardware logic as part of the data transfer control circuit is most suitable.
Some hardware configurations which attempt to solve this problem comprise a microprocessor and necessary support components. Such solutions are inefficient for a small number of data terminals since the entire microprocessor configuration must be provided even for a single data terminal. Other hardware configurations control the data transfer by timing components. Such solutions are small in size and may be modular but, are subject to high failure rates inherent in multiple stage timing devices due to the multiplying of timing tolerances.
Another solution is shown in FIG. 2. FIG. 2 shows the data processing system connected to a FIFO data buffer 10 and a universal asynchronous receiver/transmitter 51 connected to the data buffer 10 and to a data terminal. The control circuit logic comprising gates 21-25, JK flip-flop 30, five bit shift register 40 and gates 41-45 is connected between the data buffer 10 and the universal asynchronous receiver/transmitter (UART) 51. This solution employs a 5 bit shift register 40 for controlling the sequence of operations. The latches comprised of gates 21-24, gate 25 and JK flip-flop 30 provide the timing intervals between the control pulses and determine the duration of these pulses. The shortcoming of this solution is that it would require 18 integrated circuit packages in addition to the FIFO buffer and UART. Furthermore, the solution would require seven separate integrated circuit device types. Still further, this circuit exhibits the timing difficulties mentioned above due to the use of the shift register.
Accordingly, it is the object of the present invention to provide a minimally sized automatic asynchronous bidirectional interface between a high speed data processing system and a data terminal device.
It is another object of the present invention to provide a data transfer control circuit which minimizes the amount of dead-time of the data processing system while transmitting to a data terminal.
It is further object of the present invention to minimize the number of times that protocol must be established between the data processor and a particular data terminal.
It is yet another object of the present invention to provide a modular configuration which may grow efficiently according to the number of data terminals in the data processing system.